Syllabus VLSI DESIGN R13 Regulation B.Tech JNTUK-kakinada Syllabus download

Syllabus , VLSI DESIGN, R13 Regulation, B.Tech , JNTUK,Syllabus, download,

VLSI DESIGN Syllabus R13 Regulation RT41028

Unit - I

Introduction Introduction to IC technology – The IC era – MOS and related VLSI technology – Basic MOS transistors – Enhancement and depletion modes of transistor action – IC production process – MOS and CMOS fabrication process – BiCMOS technology – Comparison b/w CMOS and bipolar technologies.

Unit - II

Basic electrical properties of MOS and BiCMOS circuits Ids–Vds relationships – Aspects of MOS transistor threshold voltage – MOS Trans–conductance and output conductance – MOS Transistor – Figure of merit – The pMOS transistor – The nMOS inverter – Determination of pull– up to pull–down ratio for nMOS inverter driven by another nMOS inverter for an nMOS inverter driven through one or more pass Transistors – Alternative forms of pull up – The CMOS Inverter MOS transistor Circuit model – Bi–CMOS Inverters.

Unit - III

MOS and BiCOMS circuit design processes MOS layers – Stick diagrams – Design rules and layout – General observation on the design rules, 2?m double metal, double poly – CMOS/BiCMOS rules, 1.2?m Double metal, Double poly CMOS rules – Layout diagrams of NAND and NOR gates and CMOS inverter – Symbolic Diagrams – Translation to Mask Form.

Unit - IV

Basic circuit concepts Sheet resistance – Sheet resistance concept applied to MOS transistor and inverters – Area capacitance of layers – Standard unit of capacitance – Some area capacitance calculations – The delay unit – Inverter delays – Driving large capacitive loads – Propagations Delays – Wiring Capacitance – Fan–in and Fan–out characteristics – Choice of layers – Transistor switches – Realization of gates using nMOS, pMOS and CMOS technologies.

Unit - V

Scaling of MOS circuit Scaling models and scaling factors – Scaling factors for device parameters – Limitations of scaling – Limits due to sub threshold currents – Limits on logic level and supply voltage due to noise – Limits due to current density – Some architectural Issues – Introduction to switch logic and gate logic.

Unit - VI

Digital design using HDL Digital system design process – VLSI Circuit Design Process – Hardware simulation – Hardware Synthesis – History of VHDL – VHDL requirements – Levels of abstraction – Elements of VHDL – Packages – Libraries and bindings – Objects and classes – Variable assignments – Sequential statements – Usage of subprograms – Comparison of VHDL and verilog HDL. VHDL MODELLING Simulation – Logic Synthesis – Inside a logic synthesizer – Constraints – Technology libraries – VHDL and logic synthesis – Functional gate – Level verification – Place and route – Post layout timing simulation – Static timing – Major net list formats for design representation – VHDL synthesis – Programming approach.

Text Books

1. Essentials of VLSI Circuits and Systems–Kamran Eshraghian, Douglas and A.Pucknell and Sholeh Eshraghian, Prentice–Hall of India Private Limited, 2005 Edition.
2. VLSI Design–K. Lal Kishor and V.S.V.Prabhakar, I.K. International Publishing House Private Limited, 2009 First Edition.
3. VLSI Design–A.Shanthi and A.Kavitha, New Age International Private Limited, 2006 First Edition.

Reference Books

1. VLSI Design By Debaprasad Das, Oxford University Press,2010.
2. VLSI Design By A.Albert Raj & T. Latha, PHI Learning Private Limited, 2010.

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